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While debugging why USB wouldn't work when I used the SAI PLL to generate the 48MHz, I found out that the bits for CK48MSEL and SDIOSEL are assigned to register "DCKCFGR" instead of the correct one, "DCKCFGR2", resulting in the clock mux for 48Mhz to not be set correctly.
I do not know enough about how the code generation works for embassy to submit a fix for it myself, but I worked around it by doing the following in /embassy-stm32/src/rcc/f247.rs:
I had to also keep the bits being assigned to the wrong register as well as the correction, because there is a check that causes a panic if they aren't set (so that check probably needs to be adjusted as well)
Luckily those bits effect a different mux I am not using.
The text was updated successfully, but these errors were encountered:
While debugging why USB wouldn't work when I used the SAI PLL to generate the 48MHz, I found out that the bits for CK48MSEL and SDIOSEL are assigned to register "DCKCFGR" instead of the correct one, "DCKCFGR2", resulting in the clock mux for 48Mhz to not be set correctly.
I do not know enough about how the code generation works for embassy to submit a fix for it myself, but I worked around it by doing the following in /embassy-stm32/src/rcc/f247.rs:
I had to also keep the bits being assigned to the wrong register as well as the correction, because there is a check that causes a panic if they aren't set (so that check probably needs to be adjusted as well)
Luckily those bits effect a different mux I am not using.
The text was updated successfully, but these errors were encountered: