Ferguson BigBoard II

[zx70]

I suppose this relevant quantity of code was a @Robbbert contribution.
The current comment says: "2009-05-12 Skeleton driver", but the overall structure seems to be very close to a working status, it is possible to get the console somehow working with minor edits.

In the comment Robbert wrote:
ToDo:
- Finish floppy disk support (i have no boot disk)

..but now the boot disks are available:
http://bitsavers.org/bits/Ferguson/Big_Board_II/

The files with .S1 and .S2 extensions are valid IMD files.

... and even more interesting, a file named "bigboardII_romMonSrc.img" includes useful information:

		(...)
	LD	HL,DOSTEP	;START STEPPER FINITE STATE MACHINE
	LD	(STPVEC),HL
	LD	A,(SELCPY)
	RES	3,A		;MAKE 179X TEST INPUT LOW TO DISABLE
	OUT	(SELMUX),A	; INTERNAL OPERATION TIME DELAYS
	LD	A,10000001B
	OUT	(CTCB2),A	;START CTC 1 MILLISECOND INTERRUPT
STEP3:	LD	A,(STPCNT)
	OR	A
	JR	NZ,STEP3	;LOOP UNTIL STEP COUNTER REACHES ZERO
	LD	A,(SELCPY)
	SET	3,A		;TAKE 179X TEST PIN BACK HIGH
	OUT	(SELMUX),A

STEP4:	CALL	VERIFY		;ELSE READ AN ID-MARK TO VERIFY SEEK
STEPX:	RET

The most interesting part is in this image file only, it was never extracted:

;
;
ON	EQU	00001000B
OFF	EQU	00000000B
;
;	BIT ASSIGNMENTS FOR LATCH 'U14'
;
BUZZER	EQU	7
MOTOR	EQU	6
HLDTIM	EQU	5
DIO DATA PORT B
SIOCPB	EQU	SIO+3		;SIO CONTROL/STATUS PORT B
;
;
CTCA0	EQU	CTCA		;CTC A CHANNEL 0 (KEYBOARD STROBE)
CTCA1	EQOUNTER MODE
	DEFB	0		;COUNT INDEX PULSES MODULO-256
;
;
	DEFB	1,CTCB0
	DEFB	CTCBV		;BASE INTERRUPT VECTOR FOR CTC B

	DEFUDRATES AND TIMERS
DMA	EQU	8CH		;Z80 DMA CONTROLLER
PORT3	EQU	0C0H		;MEMORY CONTROL 74LS259
SENSE	EQU	0C4H		;SENSE INPUTS 74LRT3
	DEFB	ATTEN+ON	;ATTRIBUTE ENABLE ON
	DEFB	FDCRST+ON	;179X RESET PIN HIGH

	DEFB	1,SELMUX
	DEFB	00001010B	;ALL DRIVES OFUMBER
	JR	NZ,CRCG1
	LD	A,H
	OR	L		;HL SHOULD=0 IF VALID CRC16
	RET
;
;
;
;
INITCRT:
	LD	B,16		;WRITE TO 16 REGISTERS IDEN	EQU	4
SMC2	EQU	3
SMC1	EQU	2
SIDSEL	EQU	1
DYSTAT	EQU	0
;
;
;	BIT ASSIGNMENTS FOR LATCH 'U41'
;
ATTEN	EQU	7		;ATTRIBUU	CTCA+1		;CTC A CHANNEL 1 (INDEX PULSE COUNT)
CTCA2	EQU	CTCA+2		;CTC A CHANNEL 2 (SIO A SYNC INTERRUPT)
CTCA3	EQU	CTCA+3		;CTB	2,CTCB0
	DEFB	01000111B	;PUT CTC0 IN COUNTER MODE
	DEFB	128		;DIVIDE BY 128 GIVES 300 BAUD FOR SIO B

	DEFB	2,CTCB1
	DEFBS244
PORT0	EQU	0C8H		;MISC CONTROL BITS 74LS259
SELMUX	EQU	0CCH		;DRIVE SELECT/DMA MUX 74LS273
KBD	EQU	0D0H		;KEYBOARD INPUTSF, /TEST=1, DRQ->RDY
;
;
;	DO SOFTWARE RESET OF DMA AS RECOMENDED BY ZILOG
;
	DEFB	6,DMA
	DEFB	11000011B
	DEFB	11000011B
N 6845
	LD	C,0
INCRT1:	LD	A,C
	OUT	(CRTADD),A	;OUTPUT REGISTER NUMBER TO CRTC
	LD	A,(HL)
	INC	HL
	OUT	(CRTDAT),A	;OUTPUT DTE ENABLE PIN
FDCRST	EQU	6		;DISK CONTROLLER RESET
STDBB	EQU	5		;STD/BETTERBOARD BANK SELECT
VPP	EQU	4		;PROM VPP ENABLE
PGMC A CHANNEL 3 (VSYNC INTERRUPT)
;
;
CTCB0	EQU	CTCB		;CTC B CHANNEL 0 (SIO A BAUDRATE)
CTCB1	EQU	CTCB+1		;CTC B CHANNEL 1 (SI	01000111B	;PUT CTC1 IN COUNTER MODE
	DEFB	128		;DIVIDE BY 128 GIVES 300 BAUD FOR SIO A

	DEFB	2,CTCB2
	DEFB	00000111B	;PUT  74LS373
WD179X	EQU	0D4H		;WESTERN DIGITAL DISK CONTROLLER
GENPIO	EQU	0D8H		;GENERAL PURPOSE PARALLEL PORTS
CRTC	EQU	0DCH		;6
	DEFB	11000011B
	DEFB	11000011B
	DEFB	11000011B
	DEFB	11000011B
;
;
;	PROGRAM CTC A AND B FOR VARIOUS INTERRUPT
;	AND TIATA TO SELECTED REGISTER
	INC	C
	DJNZ	INCRT1
	RET
;
;
;
;
	PAGE
;
;
;	... INPUT/OUTPUT PORT EQUATES AND INITIALIZATIO	EQU	3		;PROM PGM ENABLE
OEVPP	EQU	2		;PROM OE/VPP SWITCH
DECODE	EQU	1		;BYTEWIDE MEMORY DECODE CONTROL
OUTEN	EQU	0		;BYTEWIDO B BAUDRATE)
CTCB2	EQU	CTCB+2		;CTC B CHANNEL 2 (1 MILLISECOND TIMER)
CTCB3	EQU	CTCB+3		;CTC B CHANNEL 3 (CLOCK INTERRUPT)
;CTC2 IN TIMER MODE
	DEFB	250		;PULSE EVERY 250*4 MICROSECONDS

	DEFB	2,CTCB3
	DEFB	11000111B	;PUT CTC3 IN COUNTER MODE
	DEF845 CRT CONTROLLER
;
;
SIODPA	EQU	SIO+0		;SIO DATA PORT A
SIOCPA	EQU	SIO+1		;SIO CONTROL/STATUS PORT A
SIODPB	EQU	SIO+2		;SMING FUNCTIONS
;
	DEFB	1,CTCA0
	DEFB	CTCAV		;BASE INTERRUPT VECTOR FOR CTC A

	DEFB	2,CTCA1
	DEFB	01000111B	;PUT CTC1 IN CN TABLES ...
;
;
SIO	EQU	80H		;DUAL SERIAL I/O
CTCA	EQU	84H		;CTC FOR KEYBOARD/FDC/SIO INTERRUPTS
CTCB	EQU	88H		;CTC FOR BAE MEMORY /OE CONTROL
;
;
;
;
IOTAB	EQU	$		;I/O INITIALIZATION TABLE
;
;	INITIALIZATION FOR TTL BIT LATCHES
;
	DEFB	2,POB	250		;INTERRUPT EVERY 250 MILLISECONDS
;
;
;	INITIALIZE SIO CHANNEL A AND B FOR ASYNCHRONOUS SERIAL
;	INTERFACE TO PRINTER100000B	;CURSOR START RASTER
	DEFB	0		;CURSOR END RASTER
	DEFB	0		;START ADDRESS MSB
	DEFB	0		;START ADDRESS LSB
	DEFB	0		;C0B	;REVERSE VIDEO
UNDLINE	EQU	00001000B	;UNDERLINE
STRIKE	EQU	00000100B	;STRIKETHRU
;
;	INITIALIZATION FOR 80*24 DISPLAY USI;********************************************************
;*							*
;*	INTERRUPT SERVICE ROUTINES FOR KEYBOARD		*
;*	INPUT A00B	;INTERRUPTS OFF
	DEFB	3		;SELECT REGISTER #3
	DEFB	01000001B	;7 BITS/RX CHARACTER
	DEFB	5		;SELECT REGISTER #5
	DEFB	101FB	0		;CURSOR END RASTER
	DEFB	0		;START ADDRESS MSB
	DEFB	0		;START ADDRESS LSB
	DEFB	0		;CURSOR ADDRESS MSB
	DEFB	0		;CURS OR TERMINAL
;
	DEFB	10,SIOCPB
	DEFB	4		;SELECT REGISTER #4
	DEFB	01000101B	;16X CLOCK, 1 STOP BIT
	DEFB	1		;SELECT REGISTEURSOR ADDRESS MSB
	DEFB	0		;CURSOR ADDRESS LSB
;
;
;	INITIALIZATION FOR 80*24 DISPLAY USING 16 Mhz CLOCK
;	AND 9 DOT BY 12 NG 11 MHZ CLOCK
;	AND 7 DOT BY 10 RASTER CHARACTER CELL SIZE
;
M1TAB:	DEFB	99		;HORIZ TOTAL-1
	DEFB	80		;HORIZ DISPLAYED
	DND REAL-TIME CLOCK FUNCTIONS		*
;*							*
;********************************************************
;

...etc

Note the references in the code to LATCH 'U14' and LATCH 'U41', e.g. the "syslatch2" object (SYS2 line in the diagram) should be somehow related to the SELMUX port mentioned here.

Another relevant point, in the Robert's notes:

Difficulties encountered:
The FDC has a INTRQ pin, the diagram says it goes to page 6, but it just vanishes instead.

I think it this document should help in understanding the way it works.

The "Elektuur" articles:
http://retro.hansotten.nl/uploads/z80/elektuurbigboardii.zip

... describe the detail of both SYS1 and SYS2 lines.

This part (courtesy of Google Translate) should help:

SYS2 system-control-port 2
SYS2 (U-13) is the second control port

This controls the four floppy disk select lines, the floppy disk test pin, and the addresses for the DMA-ready multiplexer (U-12).
Like SYS1, SYS2 is also a write-only port.

DMA-ready MUX addresses:
The lowest three bits of SYS2 are the DMA multiplexer addresses. Figure 3 shows which peripheral chips are routed to the RDY terminal of the DMA controller U-62 (schematic sheet 2).

TEST:
Bit 3 is connected to the TEST input of the floppy controller U-10 (schematic sheet 5).
If this bit is "0", all internal time delays in the floppy controller are set to minimum.
Normally TEST is "1" Only with fast track changes (track seek) TEST becomes "0" momentarily.

DSO... DS3:
Bit 7...4 (note: order is reversed!) are the four drive-select lines.
With a little tinkering in the ROM monitor and with a multiplexer on these lines, a maximum of 16 drives can be selected.

[Robbbert]

I haven't done any meaningful work on this for 7 years, and I'm no longer involved with it.

If you want this information included, you should push it along, make a PR.

[zx70]

Thank you for answering !
The problem is I'm terrible with C++ programming and MAME macros, so I chose to wrap up what i could understand while I was peeping at the code, but maybe I'll find the way :)
It was a big amount of work, it is a pity to leave it behind.