fix potential race condition in boot-cypress #19
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purdeaandrei
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You should be able to easily test the change with a Glasgow, since for the purpose of the bootloader it's just like any other devboard with a 2-address-byte EEPROM. Sounds good? |
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This PR depends on PR #18
IMPORTANT: I have not tested this change,
Note that I have tested similar changes in glasgow firmware, with success (will send a PR for that soon).
Note that this also potentially fixes any errors going unnoticed.
If we set HSNAK when we arm the buffer, the host will complete its status stage as soon as it sends the data stage, and will not wait for
eeprom_writeto finish. TheSTALL_EP0()call that we execute on line 154, will not have an effect, because the following setup packet will clear it (this is how the FX2 works), so this error would go undetected by the host!Note that this change should still be tested before being merged, because before this change,
the firmware was not sensitive to potential spurious errors returned by eeprom_write.
If
eeprom_writehad a spurious errors problem, then this PR could introduce a regression,so I suggest not merging this PR without testing it first.
Note that
STALL_EP0()already setsHSNAK, so it's not necessary to callACK_EP0();on failure.